[LoongArch][NFC] Pre-commit tests for vector type isLegalAddressingMode implementation

llvm/test/CodeGen/LoongArch/lasx/loop-reduce.ll

@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 -mattr=+lasx --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+;; Modified based on llvm-test-suite:
+;; SingleSource/Regression/C/gcc-c-torture/execute/pr56837.c
+
+@a = dso_local local_unnamed_addr global [1024 x { i32, i32 }] zeroinitializer, align 4
+
+define dso_local void @foo() local_unnamed_addr {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lu12i.w $a0, -2
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT:    xvld $xr0, $a1, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI0_1)
+; CHECK-NEXT:    xvld $xr1, $a1, %pc_lo12(.LCPI0_1)
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(a)
+; CHECK-NEXT:    addi.d $a1, $a1, %pc_lo12(a)
+; CHECK-NEXT:    lu12i.w $a2, 2
+; CHECK-NEXT:    .p2align 4, , 16
+; CHECK-NEXT:  .LBB0_1: # %vector.body
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    add.d $a3, $a1, $a0
+; CHECK-NEXT:    xvldx $xr2, $a3, $a2
+; CHECK-NEXT:    xvpermi.d $xr3, $xr2, 78
+; CHECK-NEXT:    xvori.b $xr4, $xr0, 0
+; CHECK-NEXT:    xvshuf.d $xr4, $xr0, $xr3
+; CHECK-NEXT:    xvori.b $xr3, $xr1, 0
+; CHECK-NEXT:    xvshuf.w $xr3, $xr4, $xr2
+; CHECK-NEXT:    addi.d $a0, $a0, 16
+; CHECK-NEXT:    xvstx $xr3, $a3, $a2
+; CHECK-NEXT:    bnez $a0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %for.end
+; CHECK-NEXT:    ret
+entry:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds nuw [1024 x { i32, i32 }], ptr @a, i64 0, i64 %index
+  %a = load <8 x i32>, ptr %0, align 4
+  %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 1, i32 7, i32 poison, i32 0, i32 poison, i32 poison, i32 3, i32 5>
+  store <8 x i32> %b, ptr %0, align 4
+  %index.next = add nuw i64 %index, 2
+  %1 = icmp eq i64 %index.next, 1024
+  br i1 %1, label %for.end, label %vector.body
+
+for.end:                                          ; preds = %vector.body
+  ret void
+}

llvm/test/CodeGen/LoongArch/lsx/loop-reduce.ll

@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+;; Modified based on llvm-test-suite:
+;; SingleSource/Regression/C/gcc-c-torture/execute/pr56837.c
+
+@a = dso_local local_unnamed_addr global [1024 x { i32, i32 }] zeroinitializer, align 4
+
+define dso_local void @foo() local_unnamed_addr {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lu12i.w $a0, -2
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(a)
+; CHECK-NEXT:    addi.d $a1, $a1, %pc_lo12(a)
+; CHECK-NEXT:    lu12i.w $a2, 2
+; CHECK-NEXT:    .p2align 4, , 16
+; CHECK-NEXT:  .LBB0_1: # %vector.body
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    add.d $a3, $a1, $a0
+; CHECK-NEXT:    vldx $vr0, $a3, $a2
+; CHECK-NEXT:    vshuf4i.w $vr0, $vr0, 9
+; CHECK-NEXT:    addi.d $a0, $a0, 16
+; CHECK-NEXT:    vstx $vr0, $a3, $a2
+; CHECK-NEXT:    bnez $a0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %for.end
+; CHECK-NEXT:    ret
+entry:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds nuw [1024 x { i32, i32 }], ptr @a, i64 0, i64 %index
+  %a = load <4 x i32>, ptr %0, align 4
+  %b = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 2, i32 poison, i32 0>
+  store <4 x i32> %b, ptr %0, align 4
+  %index.next = add nuw i64 %index, 2
+  %1 = icmp eq i64 %index.next, 1024
+  br i1 %1, label %for.end, label %vector.body
+
+for.end:                                          ; preds = %vector.body
+  ret void
+}