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[NVVM][NVPTX] Add support for tcgen05.mma #151949

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[NVVM][NVPTX] Add support for tcgen05.mma #151949

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388 changes: 385 additions & 3 deletions llvm/docs/NVPTXUsage.rst
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430 changes: 429 additions & 1 deletion llvm/include/llvm/IR/IntrinsicsNVVM.td
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9 changes: 9 additions & 0 deletions llvm/include/llvm/IR/NVVMIntrinsicUtils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,15 @@ enum class CTAGroupKind : uint8_t {
CG_2 = 2, // cta_group::2 modifier
};

enum class Tcgen05MMAKind : uint8_t { F16 = 0, TF32 = 1, F8F6F4 = 2, I8 = 3 };

enum class Tcgen05CollectorUsageOp : uint8_t {
DISCARD = 0,
LASTUSE = 1,
FILL = 2,
USE = 3,
};

inline bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
switch (IntrinsicID) {
case Intrinsic::nvvm_f2i_rm_ftz:
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313 changes: 313 additions & 0 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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39 changes: 38 additions & 1 deletion llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,44 @@ enum NodeType : unsigned {
StoreV2,
StoreV4,
StoreV8,
LAST_MEMORY_OPCODE = StoreV8,
TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SHARED_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SHARED_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SHARED_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SHARED_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
TCGEN05_MMA_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
TCGEN05_MMA_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_SHARED_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_SHARED_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_SHARED_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_SHARED_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
TCGEN05_MMA_SP_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1,
TCGEN05_MMA_SP_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2,
TCGEN05_MMA_SP_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_SP_TENSOR_F16_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
TCGEN05_MMA_SP_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT,
TCGEN05_MMA_SP_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
LAST_MEMORY_OPCODE =
TCGEN05_MMA_SP_TENSOR_TF32_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT,
};
}

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