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[GlobalISel] Add computeNumSignBits for SHL #152067

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[GlobalISel] Add computeNumSignBits for SHL #152067

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[GlobalISel] Add computeNumSignBits for SHL
yichi170 Aug 4, 2025
16f4688
Update test and comment
yichi170 Aug 6, 2025
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38 changes: 38 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1892,6 +1892,44 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
FirstAnswer = std::min<uint64_t>(FirstAnswer + *C, TyBits);
break;
}
case TargetOpcode::G_SHL: {
Register Src1 = MI.getOperand(1).getReg();
Register Src2 = MI.getOperand(2).getReg();
if (std::optional<ConstantRange> ShAmtRange =
getValidShiftAmountRange(Src2, DemandedElts, Depth + 1)) {
uint64_t MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();
uint64_t MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();

MachineInstr &ExtMI = *MRI.getVRegDef(Src1);
unsigned ExtOpc = ExtMI.getOpcode();

// Try to look through ZERO/SIGN/ANY_EXTEND. If all extended bits are
// shifted out, then we can compute the number of sign bits for the
// operand being extended. A future improvement could be to pass along the
// "shifted left by" information in the recursive calls to
// ComputeKnownSignBits. Allowing us to handle this more generically.
if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||
ExtOpc == TargetOpcode::G_ANYEXT) {
LLT ExtTy = MRI.getType(Src1);
Register Extendee = ExtMI.getOperand(1).getReg();
LLT ExtendeeTy = MRI.getType(Extendee);
uint64_t SizeDiff =
ExtTy.getScalarSizeInBits() - ExtendeeTy.getScalarSizeInBits();

if (SizeDiff <= MinShAmt) {
unsigned Tmp =
SizeDiff + computeNumSignBits(Extendee, DemandedElts, Depth + 1);
if (MaxShAmt < Tmp)
return Tmp - MaxShAmt;
}
}
// shl destroys sign bits, ensure it doesn't shift out all sign bits.
unsigned Tmp = computeNumSignBits(Src1, DemandedElts, Depth + 1);
if (MaxShAmt < Tmp)
return Tmp - MaxShAmt;
}
break;
}
case TargetOpcode::G_TRUNC: {
Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src);
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182 changes: 182 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
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@@ -0,0 +1,182 @@
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s

---
name: Cst
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Can you also add test cases for the transformed added above, like shl(zext) and shl(sext). I think it should be able to add tests for shl(<something with sign bits>, C) too, so maybe shl(ashr(X, C1), C2)

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I updated the test. Let me know if it doesn't align with what you expect!

body: |
bb.1:
; CHECK-LABEL: name: @Cst
; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %2:_ KnownBits:10000000 SignBits:1
%0:_(s8) = G_CONSTANT i8 224
%1:_(s8) = G_CONSTANT i8 2
%2:_(s8) = G_SHL %0, %1
...
---
name: CstBig
body: |
bb.1:
; CHECK-LABEL: name: @CstBig
; CHECK-NEXT: %0:_ KnownBits:11111001 SignBits:5
; CHECK-NEXT: %1:_ KnownBits:00000110 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:01000000 SignBits:1
%0:_(s8) = G_CONSTANT i8 249
%1:_(s8) = G_CONSTANT i8 6
%2:_(s8) = G_SHL %0, %1
...
---
name: CstSext
body: |
bb.1:
; CHECK-LABEL: name: @CstSext
; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
; CHECK-NEXT: %3:_ KnownBits:00000011 SignBits:6
; CHECK-NEXT: %4:_ KnownBits:11000000 SignBits:2
%0:_(s8) = G_CONSTANT i8 129
%1:_(s8) = G_CONSTANT i8 4
%2:_(s8) = G_ASHR %0, %1
%3:_(s8) = G_CONSTANT i8 3
%4:_(s8) = G_SHL %2, %3
...
---
name: CstSextBig
body: |
bb.1:
; CHECK-LABEL: name: @CstSextBig
; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
; CHECK-NEXT: %3:_ KnownBits:00000110 SignBits:5
; CHECK-NEXT: %4:_ KnownBits:00000000 SignBits:8
%0:_(s8) = G_CONSTANT i8 129
%1:_(s8) = G_CONSTANT i8 4
%2:_(s8) = G_ASHR %0, %1
%3:_(s8) = G_CONSTANT i8 6
%4:_(s8) = G_SHL %2, %3
...
---
name: ScalarVar
body: |
bb.1:
; CHECK-LABEL: name: @ScalarVar
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
%0:_(s8) = COPY $b0
%1:_(s8) = COPY $b1
%2:_(s8) = G_SHL %0, %1
...
---
name: ScalarCst
body: |
bb.1:
; CHECK-LABEL: name: @ScalarCst
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
; CHECK-NEXT: %2:_ KnownBits:?????000 SignBits:1
%0:_(s8) = COPY $b0
%1:_(s8) = G_CONSTANT i8 3
%2:_(s8) = G_SHL %0, %1
...
---
name: VectorVar
body: |
bb.1:
; CHECK-LABEL: name: @VectorVar
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
%2:_(<4 x s16>) = G_SHL %0, %1
...
---
name: VectorCst
body: |
bb.1:
; CHECK-LABEL: name: @VectorCst
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %3:_ KnownBits:?????????????000 SignBits:1
%0:_(<4 x s16>) = COPY $d0
%1:_(s16) = G_CONSTANT i16 3
%2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
%3:_(<4 x s16>) = G_SHL %0, %2
...
---
name: VectorCst36
body: |
bb.1:
; CHECK-LABEL: name: @VectorCst36
; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
; CHECK-NEXT: %4:_ KnownBits:000000????????00 SignBits:7
%0:_(s16) = G_CONSTANT i16 3
%1:_(s16) = G_CONSTANT i16 6
%2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
%3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
%4:_(<4 x s16>) = G_SHL %2, %3
...

---
name: VectorCst3unknown
body: |
bb.1:
; CHECK-LABEL: name: @VectorCst3unknown
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
%0:_(<4 x s16>) = COPY $d0
%2:_(s16) = COPY $h0
%1:_(s16) = G_CONSTANT i16 3
%3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
%4:_(<4 x s16>) = G_SHL %0, %3
...
---
name: VectorSext
body: |
bb.1:
; CHECK-LABEL: name: @VectorSext
; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %4:_ KnownBits:0000000000000110 SignBits:13
; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13
; CHECK-NEXT: %6:_ KnownBits:1111??11?????000 SignBits:5
%0:_(s8) = G_CONSTANT i8 238
%1:_(s16) = G_SEXT %0(s8)
%2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
%3:_(s16) = G_CONSTANT i16 3
%4:_(s16) = G_CONSTANT i16 6
%5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
%6:_(<4 x s16>) = G_SHL %2, %5
...
---
name: VectorSextBig
body: |
bb.1:
; CHECK-LABEL: name: @VectorSextBig
; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
; CHECK-NEXT: %3:_ KnownBits:0000000000001000 SignBits:12
; CHECK-NEXT: %4:_ KnownBits:0000000000001001 SignBits:12
; CHECK-NEXT: %5:_ KnownBits:000000000000100? SignBits:12
; CHECK-NEXT: %6:_ KnownBits:11??11?000000000 SignBits:2
%0:_(s8) = G_CONSTANT i8 238
%1:_(s16) = G_SEXT %0(s8)
%2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
%3:_(s16) = G_CONSTANT i16 8
%4:_(s16) = G_CONSTANT i16 9
%5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
%6:_(<4 x s16>) = G_SHL %2, %5
...
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