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[LoongArch] Enable vector tests for 32-bit target #152094

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[LoongArch] Enable vector tests for 32-bit target #152094

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101 changes: 79 additions & 22 deletions llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
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Original file line number Diff line number Diff line change
@@ -1,16 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64

; TODO: Load a element and splat it to a vector could be lowerd to xvldrepl

; A load has more than one user shouldn't be lowered to xvldrepl
define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) {
; CHECK-LABEL: should_not_be_optimized:
; CHECK: # %bb.0:
; CHECK-NEXT: ld.d $a0, $a0, 0
; CHECK-NEXT: xvreplgr2vr.d $xr0, $a0
; CHECK-NEXT: st.d $a0, $a1, 0
; CHECK-NEXT: ret
; LA32-LABEL: should_not_be_optimized:
; LA32: # %bb.0:
; LA32-NEXT: ld.w $a2, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: st.w $a2, $a1, 0
; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 0
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 2
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 4
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 6
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
; LA32-NEXT: st.w $a0, $a1, 4
; LA32-NEXT: ret
;
; LA64-LABEL: should_not_be_optimized:
; LA64: # %bb.0:
; LA64-NEXT: ld.d $a0, $a0, 0
; LA64-NEXT: xvreplgr2vr.d $xr0, $a0
; LA64-NEXT: st.d $a0, $a1, 0
; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
store i64 %tmp, ptr %dst
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
Expand All @@ -19,11 +34,25 @@ define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) {
}

define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) {
; CHECK-LABEL: xvldrepl_d_unaligned_offset:
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $a0, $a0, 4
; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvldrepl_d_unaligned_offset:
; LA32: # %bb.0:
; LA32-NEXT: ld.w $a1, $a0, 4
; LA32-NEXT: ld.w $a0, $a0, 8
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
; LA32-NEXT: ret
;
; LA64-LABEL: xvldrepl_d_unaligned_offset:
; LA64: # %bb.0:
; LA64-NEXT: addi.d $a0, $a0, 4
; LA64-NEXT: xvldrepl.d $xr0, $a0, 0
; LA64-NEXT: ret
%p = getelementptr i32, ptr %ptr, i32 1
%tmp = load i64, ptr %p
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
Expand Down Expand Up @@ -103,21 +132,49 @@ define <8 x i32> @xvldrepl_w_offset(ptr %ptr) {


define <4 x i64> @xvldrepl_d(ptr %ptr) {
; CHECK-LABEL: xvldrepl_d:
; CHECK: # %bb.0:
; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvldrepl_d:
; LA32: # %bb.0:
; LA32-NEXT: ld.w $a1, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
; LA32-NEXT: ret
;
; LA64-LABEL: xvldrepl_d:
; LA64: # %bb.0:
; LA64-NEXT: xvldrepl.d $xr0, $a0, 0
; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> poison, <4 x i32> zeroinitializer
ret <4 x i64> %tmp2
}

define <4 x i64> @xvldrepl_d_offset(ptr %ptr) {
; CHECK-LABEL: xvldrepl_d_offset:
; CHECK: # %bb.0:
; CHECK-NEXT: xvldrepl.d $xr0, $a0, 264
; CHECK-NEXT: ret
; LA32-LABEL: xvldrepl_d_offset:
; LA32: # %bb.0:
; LA32-NEXT: ld.w $a1, $a0, 264
; LA32-NEXT: ld.w $a0, $a0, 268
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
; LA32-NEXT: ret
;
; LA64-LABEL: xvldrepl_d_offset:
; LA64: # %bb.0:
; LA64-NEXT: xvldrepl.d $xr0, $a0, 264
; LA64-NEXT: ret
%p = getelementptr i64, ptr %ptr, i64 33
%tmp = load i64, ptr %p
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/LoongArch/lasx/bswap.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @bswap_v16i16(ptr %src, ptr %dst) nounwind {
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define <32 x i8> @concat_poison_v32i8_1(<16 x i8> %a) {
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @ctpop_v32i8(ptr %src, ptr %dst) nounwind {
Expand Down
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